Epitaxial lift-off process enables the separation of III–V device layers from gallium arsenidesubstrates and has been extensively explored to avoid the high cost of III–V devices by reusing the substrates. Conventional epitaxial lift-off processes require several post-processing steps to restore the substrate to an epi-ready condition. Here we present an epitaxial lift-off scheme that minimizes the amount of post-etching residues and keeps the surface smooth, leading to direct reuse of the gallium arsenide substrate. The successful direct substrate reuse is confirmed by the performance comparison of solar cells grown on the original and the reused substrates. Following the features of our epitaxial lift-off process, a high-throughput technique called surface tension-assisted epitaxial lift-off was developed. In addition to showing full wafer gallium arsenide thin film transfer onto both rigid and flexible substrates, we also demonstrate devices, including light-emitting diode and metal-oxide-semiconductor capacitor, first built on thin active layers and then transferred to secondary substrates. Figure 1: Concept of epitaxial lift-off (ELO) process and post-ELO GaAs surface morphologies with conventional and novel ELO processes. (a) Schematic illustration of general ELO process. (b,c) Schematic illustrations of the chemical reactions near the sacrificial layer/etchant interfaces during the conventional and the novel ELO process and the three-dimensional AFM ima… Figure 2: Surface morphologies of GaAs surfaces during ELO process (a) AFM images of the GaAs substrate surface dipped in both concentrated and dilutedHF and HCl for 1 day. (b,c) are the schematic illustrations of the surface chemistry of GaAs dipped in HF and HCl, respectively. Figure 3: Performance of single junction GaAs solar cells fabricated on new and reused substrates.close (a) Current density versus voltage (J–V) characteristics of GaAs SJ solar cells grown and fabricated on new (green symbols) and reused (blue symbols) substrates. Inset: solar cell performance parameters. (b) EQE of solar cells grown on… Figure 4: Surface tension-assisted ELO process. (a) Schematic illustration of the surface tension-assisted (STA) ELO process. (b) Etching rate of InAlP in HCl as the function of crystallographic direction. The maximum etching rate locates at. All the data were normalized by max… Figure 5: GaAs thin films transferred to rigid and flexible substrates. (a) Demonstrations of the transferred GaAs thin films to the rigid Substrate (left, GaAs on 4″ Si wafer. Center, GaAs on curved solid object. Right, GaAs on glass) and (b) flexible substrates (left, GaAs on tape. Right, GaAs on flexible… Figure 6: Demonstration of transferred devices via novel ELO process. (a) Transferred 2″ AlGaAs LED on 2″ Si wafer and the optical image of light emission. Scale bar, 5 cm. (b) Capacitance–Voltage (C–V) characteristics of n-GaAs MOSCAP before and after being transferred to a flexible tape. Inset: the o...
Highlights •Effects of atomic step width on the removal of sapphire and SiC wafers are studied. •The reason of effects of step width on the removal and the model are discussed. •CMP removal model of hexagonal wafer to obtain atomically smooth surface is proposed. •The variations of atomic step morphology towards defects are analyzed. •The formation mechanism of the defects is discussed. Absrtact Towards sapphire and SiC wafer, clear and regular atomic step morphology could be observed all-over the surface via AFM. However, the variations of atomic step widths and step directions are different on the whole of different wafer surfaces: that on sapphire wafer are uniform, while that on SiC wafer are distinct. The effects of atomic step width on removal rate are studied. Removal model of super-hard wafer to realize atomically ultra-smooth surface is proposed. The variations of atomic step morphology toward different defects on sapphire and SiC wafers surface are analyzed, and the formation mechanism is discussed. Keywords Chemical mechanical polishing (CMP); Sapphire; Silicon carbide (SiC); Atomic step Source:Sciencedirect For more information, please visit our website:www.powerwaywafer.com, send us email at sales@powerwaywafer.com .
The crystallinity of epitaxial graphene (EG) grown on a Hexagonal-SiC substrate is found to be enhanced greatly by capping the substrate with a molybdenum plate (Mo-plate) during vacuum annealing. The crystallinity enhancement of EG layer grown with Mo-plate capping is confirmed by the significant change of measured Raman spectra, compared to the spectra for no capping. Mo-plate capping is considered to induce heat accumulation on SiC surface by thermal radiation mirroring and raise Si partial pressure near surface by confining the sublimated Si atoms between SiC substrate and Mo-plate, which would be the essential contributors of crystallinity enhancement. Introduction Graphene is a 2D material composed of a monolayer of carbon atoms arranged in a honeycomb lattice structure1,2,3,4. Owing to its superior electron and hole mobilities, graphene has been considered to be a promising candidate material for ultra-fast electronic devices operating in THz frequency regime5. The first successful isolation of graphene was achieved by mechanically exfoliating highly oriented pyrolytic graphite (HOPG)2. Although high-quality single crystal graphene flakes can be obtained by mechanical exfoliation, the sizes of graphene flakes are too small (<100 μm) for practical applications6. Several alternatives including chemical vapor deposition (CVD)7,8, solid source deposition9,10, and surface graphitation of SiC4,6,11,12,13,14 have been explored for the synthesis of large-scale graphene. Of particular interest is the surface graphitation of a single crystalline SiC by thermal annealing in ultra high vacuum (UHV)4 or Ar environment6 at high temperature (>1300°C). In this process, only Si atoms are sublimated from the surface and the remaining C atoms rearrange to form a sample-size uniform so-called epitaxial graphene (EG) either on Si-face (0001) or C-face (000-1) surface15. The EG grown on C-face surface is normally thicker (typically 10–20 layers) than that on Si-face surface but its carrier mobility can reach as high as 18,700 cm2V−1s−1 14. Hass et al.showed from first-principles calculations that such high carrier mobility of C-face EG is due to the unique rotational stacking faults residing in C-face EG16. These rotational stacking faults decouple the adjacent graphene layers electronically and make the multiple graphene layers maintain the electronic properties of an isolated single layer graphene. Very recently, Trabelsi et al. have reported that a few or even single layer of graphene could be grown epitaxially on C-face surface in the form of islands (hundreds of μm) or freestanding bubbles (several μm)17, 18. Their results imply that it is possible to control the thickness of EG grown on C-face surface by carefully adjusting the Si flux supplied externally and the growth time during the conventional UHV annealing. Based on the large-scale availability and good electrical properties, the EG on SiC surface (either Si-face or C-face) clearly demonstrate...
We have used MBE to grow in AlN/GaN superlattices, with different number of periods, on 2.5-μm-thick MOVPE-GaN templates to study the development of defects such as surface deformation due to strain. After growth the samples were studied by atomic force microscopy (AFM), transmission electron microscopy (TEM), XRD and Fourier transform infrared spectroscopy (FT-IR). The strain increased with the number of quantum wells (QWs) and eventually caused defects such as microcracks visible by optical microscopy at four or more QW periods. High-resolution TEM images showed shallow recessions on the surface (surface deformation) indicating formation of microcracks in the MQW region. The measured intersubband (IS) absorption linewidth from a four period structure was 97 meV, which is comparable with the spectrum from a 10 period structure at an absorption energy of ∼700 meV. This indicates that the interface quality of the MQW is not substantially affected by the presence of cracks. Keywords Intersubband; GaN; MBE; Surface cracks; Sapphire substrate; Template Source:Sciencedirect For more information, please visit our website:www.powerwaywafer.com, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com.
The epitaxy optimization studies of high-quality n-type AlInN alloys with different indium contents grown on two types of substrates by metalorganic vapor phase epitaxy (MOVPE) were carried out. The effect of growth pressure and V/III molar ratio on growth rate, indium content, and surface morphology of these MOVPE-grown AlInN thin films were examined. The surface morphologies of the samples were characterized by scanning electron microscopy and atomic force microscopy. By varying the growth temperatures from 860 °C to 750 °C, the indium contents in AlInN alloys were increased from 0.37% up to 21.4% as determined by X-ray diffraction (XRD) measurements. The optimization studies on the growth conditions for achieving nearly-lattice-matched AlInN on GaN templates residing on sapphire and free-standing GaN substrates were performed, and the results were analyzed in a comparative way. Several applications of AlInN alloy for thermoelectric and light-emitting diodes are also discussed. Highlights ► MOVPE growth optimization of AlInN alloy on GaN template and free-standing substrate. ► Lower growth pressure and higher V/III ratio led to improved AlInN material quality. ► Lower growth temperature led to higher In-content with 780 °C to achieve Al0.83In0.17N. ► The use of GaN native substrate results in reduced material surface roughness and defects. ► The potential of AlInN for LEDs and thermoelectric applications are presented. Keywords A3. Metalorganic vapor phase epitaxy; B1. Nitrides; B2. Semiconducting III–V materials; B3. Light emitting diodes Source:Sciencedirect For more information, please visit our website:www.powerwaywafer.com, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com.
Highlights •Elaboration of a smooth 3C–SiC membrane on a SiC substrate. •Faceted surface for the (110) orientation but smoother for the (111) orientation. •Roughness of the 3C–SiC membrane limited to 9 nm for the (111) orientation. •New MEMS devices feasible. •The huge SiC properties could be entirely exploited. The cubic polytype of silicon carbide is an interesting candidate for Micro-Electro-Mechanical-Systems (MEMS) applications due to its tremendous physico-chemical properties. The recent development of multi-stacked Si/SiC heterostructures has demonstrated the possibility to obtain a (110)-oriented 3C–SiC membrane on a 3C–SiC pseudo-substrate, using a silicon layer grown by low pressure chemical vapor deposition as a sacrificial one. However, the (110) orientation of the 3C–SiC membrane led to a facetted and rough surface which could hamper its use for the development of new MEMS devices. Then, in this contribution, an optimized growth process is used to improve the surface quality of the 3C–SiC membrane. The progress relies on the mastering of a (111) orientation for the SiC film, resulting in a smooth surface. Such an optimized structure could be the starting point for the achievement of new MEMS devices in medical or harsh environment applications. Graphical abstract Keywords 3C–SiC; Micromachining; LPCVD; Micro-structure; Membrane; MEMS Source:Sciencedirect For more information, please visit our website:www.powerwaywafer.com, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com.
SiC has, during the last few years, become increasingly important as a power-device material for high voltage applications. The thick, low-doped voltage-supporting epitaxial layer is normally grown by CVD on 4° off-cut 4H-SiC substrates at a growth rate of View the MathML source using silane (SiH4) and propane (C3H8) or ethylene (C2H4) as precursors. The concentrations of epitaxial defects and dislocations depend to a large extent on the underlying substrate but can also be influenced by the actual epitaxial growth process. Here we will present a study on the properties of the epitaxial layers grown by a Cl-based technique on an a-axis (90° off-cut from c-direction) 4H-SiC substrate. Keywords 4H-SiC; a-face; DLTS; Photoluminescence; Raman; Epitaxy Source:Sciencedirect For more information, please visit our website:www.powerwaywafer.com, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com.
Nonpolar a-plane and m-plane AlN layers were grown on a-plane and m-plane 6H-SiC substrates by low-pressure hydride vapor phase epitaxy (LP-HVPE), respectively. The effects of growth temperature were investigated. Results showed that surface roughness was reduced by increasing the temperature for both a-plane and m-plane AlN layers. In-plane morphological anisotropy was revealed by scanning electron microscopy and atomic force microscopy, which was used to image the morphological and structural transitions with temperature. Anisotropy in on-axis X-ray rocking curves was also detected by high-resolution X-ray diffraction. However, compared with the a-plane AlN layer, a smooth surface was easily obtained for the m-plane AlN layer with good crystalline quality. The optimal temperature was lower for the m-plane AlN layer than that for the a-plane AlN layer. The stress characteristics of nonpolar AlN layers were studied using polarized Raman spectra. Results showed the presence of anisotropic in-plane stresses within the epitaxial nonpolar AlN layers. Keywords A1. In-plane anisotropy; A1. Nonpolar; A1. Raman spectrum; A3. Hydride vapor phase epitaxy; B2. a-plane and m-plane AlN; B2. SiC substrate Source:Sciencedirect For more information, please visit our website:www.powerwaywafer.com, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com.
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