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  • Growth and relaxation processes in Ge nanocrystals on free-standing Si(001) nanopillars

    2019-12-02

    Source:IOPscience For more information, please visit our website: www.semiconductorwafers.net, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com

  • Shock-recovery studies on InSb single crystals up to 24 GPa

    2019-11-25

    A series of shock-recovery experiments on InSb single crystals along the (100) or (111) axes up to 24 GPa were performed using flyer plate impact. The structures of recovered samples were characterized by X-ray diffraction (XRD) analysis. According to calculated peak pressures and temperatures, and phase diagram for InSb, the sample could undergo phase transitions from zinc-blende structure to high-pressure phases. However, the XRD trace of each sample corresponded to powder pattern of InSb with zinc-blende structure. The XRD trace of each sample revealed the absence of additional constituents including metastable phases and high-pressure phases of InSb except for samples shocked around 16 GPa. At 16 GPa, in addition to zinc-blende structure, additional peaks were obtained. One of these peaks may correspond to the Cmcm or Immm phase of InSb, and the other peaks were not identified. Source:IOPscience For more information, please visit our website: www.semiconductorwafers.net, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com

  • Integration of GaAs, GaN, and Si-CMOS on a common 200 mm Si substrate through multilayer transfer process

    2019-11-18

    The integration of III–V semiconductors (e.g., GaAs and GaN) and silicon-on-insulator (SOI)-CMOS on a 200 mm Si substrate is demonstrated. The SOI-CMOS donor wafer is temporarily bonded on a Si handle wafer and thinned down. A second GaAs/Ge/Si substrate is then bonded to the SOI-CMOS-containing handle wafer. After that, the Si from the GaAs/Ge/Si substrate is removed. The GaN/Si substrate is then bonded to the SOI–GaAs/Ge-containing handle wafer. Finally, the handle wafer is released to realize the SOI–GaAs/Ge/GaN/Si hybrid structure on a Si substrate. By this method, the functionalities of the materials used can be combined on a single Si platform. Source:IOPscience For more information, please visit our website: www.semiconductorwafers.net, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com

  • Highly doped p-type 3C–SiC on 6H–SiC substrates

    2019-11-11

    Highly doped p-3C–SiC layers of good crystal perfection have been grown by sublimation epitaxy in vacuum. Analysis of the photoluminescence spectra and temperature dependence of the carrier concentration shows that at least two types of acceptor centers at ~EV + 0.25 eV and at EV + 0.06–0.07 eV exist in the samples studied. A conclusion is reached that layers of this kind can be used as p-emitters in 3C–SiC devices. Source:IOPscience For more information, please visit our website: www.semiconductorwafers.net, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com

  • Photo-induced currents in CdZnTe crystals as a function of illumination wavelength

    2019-11-05

    We report variations in the currents of CdZnTe semiconductor crystals during exposure to a series of light emitting diodes of various wavelengths ranging from 470 to 950 nm. The changes in the steady-state current of one CdZnTe crystal with and without illumination along with the time dependence of the illumination effects are discussed. Analysis of the de-trapping and transient bulk currents during and after optical excitation yield insight into the behaviour of charge traps within the crystal. Similar behaviour is observed for illumination of a second CdZnTe crystal suggesting that the overall illumination effects are not crystal dependent. Source:IOPscience For more information, please visit our website: www.semiconductorwafers.net, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com

  • Room-temperature bonding of GaAs//Si and GaN//GaAs wafers with low electrical resistance

    2019-10-30

    The electrical properties of room-temperature bonded wafers made from materials with different lattice constants, such as p-GaAs and n-Si, p-GaAs and n-Si [both with an indium tin oxide (ITO) surface layer], and n-GaN and p-GaAs, were investigated. The bonded p-GaAs//n-Si sample exhibited an electrical interface resistance of 2.8 × 10−1 Ωcm2 and showed ohmic-like characteristics. In contrast, the bonded p-GaAs/ITO//ITO/n-Si sample showed Schottky-like characteristics. The bonded n-GaN//p-GaAs wafer sample exhibited ohmic-like characteristics with an interface resistance of 2.7 Ωcm2. To our knowledge, this is the first reported instance of a bonded GaN//GaAs wafer with a low electrical resistance. Source:IOPscience For more information, please visit our website: www.semiconductorwafers.net, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com

  • Epitaxial growth of Bi2Se3 layers on InP substrates by hot wall epitaxy

    2019-10-21

    The a-axis lattice parameter of Bi2Se3 is almost identical to the lattice periodicity of the InP (1 1 1) surface. We consequently obtain remarkably smooth Bi2Se3 (0 0 0 1) layers in hot-wall-epitaxy growth on InP (1 1 1)B substrates. The lattice-matched periodicity is preserved in the [1 1 0] and [] directions of the (0 0 1) surface. The Bi2Se3 layers grown on InP (0 0 1) substrates exhibit 12-fold in-plane symmetry as the [] direction of Bi2Se3 is aligned to either of the two directions. When the (1 1 1)-oriented InP substrates are inclined, the Bi2Se3 (0 0 0 1) layers are found to develop steps having a height of ~50 nm. The tilting of the Bi2Se3 [0 0 0 1] axis with respect to the growth surface is responsible for the creation of the steps. Epitaxial growth is thus evidenced to take place rather than van der Waals growth. We point out its implications on the surface states of topological insulators. Source:IOPscience For more information, please visit our website: www.semiconductorwafers.net, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com

  • Mid-infrared InAs/GaSb strained layer superlattice detectors with nBn design grown on a GaAs substrate

    2019-09-29

    We report on a type-II InAs/GaSb strained layer superlattice (SLS) photodetector (λ_{\rm cut\hbox{-}off}  ~4.3 µm at 77 K) with nBn design grown on a GaAs substrate using interfacial misfit dislocation arrays to minimize threading dislocations in the active region. At 77 K and 0.1 V of the applied bias, the dark current density was equal to 6 × 10−4 A cm−2 and the maximum specific detectivity D* was estimated to 1.2 × 1011 Jones (at 0 V). At 293 K, the zero-bias D* was found to be ~109 Jones which is comparable to the nBn InAs/GaSb SLS detector grown on the GaSb substrate. Source:IOPscience For more information, please visit our website: www.semiconductorwafers.net, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com

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