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PAM-XIAMEN Offers High Purity Semi-Insulating SiC substrate

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PAM-XIAMEN Offers High Purity Semi-Insulating SiC substrate

2018-05-02

Xiamen Powerway Advanced Material Co.,Ltd., a leading supplier of High Purity Semi-Insulating SiC substrate and other related products and services announced the new availability of size 2”&3”&4”  is on mass production in 2017. This new product represents a natural addition to PAM-XIAMEN's product line. Dr. Shaka, said, "We are pleased to offer High Purity Semi-Insulating SiC substrate to our customers. 4H Semi-Insulating Silicon Carbide (SiC) substrates that are available in on-axis orientation. The unique HTCVD crystal growth technology is the key enabler to purer products combining high and uniform resistivity with a very low defect density. The availability improve boule growth and wafering processes." and "Our customers can now benefit from the increased device yield expected when developing advanced transistors on a square substrate. Our High Purity Semi-Insulating SiC substrate are natural by products of our ongoing efforts, currently we are devoted to continuously develop more reliable products." We offer High-purity, semi-insulating (HPSI) 4H-SiC crystals with diameters up to 100 mm, which is grown by the seeded sublimation technology without the intentional deep-level element, such as vanadium dopants. And wafers cut from these crystals exhibit homogeneous activation energies near mid gap and thermally stable semi-insulating (SI) behavior (>10^7 ohm-cm) throughout device processing. Secondary ion mass spectroscopy, deep-level transient spectroscopy, optical admittance spectroscopy, and electron paramagnetic resonance data suggest that the SI behavior originates from several deep levels associated with intrinsic point defects. Micropipe densities in HPSI substrates have been demonstrated to be as low as average typical value 0.8 cm−2 in three inch diameter substrates with TTV=1.7um (median value),WARP=7.7um(median value),and BOW=-4.5um(median value).

PAM-XIAMEN's improved High Purity Semi-Insulating SiC substrate product line has benefited from strong tech, support from Native University and Laboratory Center.


Now we show you specification as follows:


HPSI, 4H SEMI-INSULATING SIC, 2″WAFER SPECIFICATION

SUBSTRATE PROPERTY

S4H-51-SI-PWAM-250 S4H-51-SI-PWAM-330 S4H-51-SI-PWAM-430

Description

A/B Production Grade  C/D Research Grade  D Dummy Grade  4H SEMI Substrate

Polytype

4H

Diameter

(50.8 ± 0.38) mm

Thickness

(250 ± 25) μm

Resistivity (RT)

>1E5 Ω·cm

Surface Roughness

< 0.5 nm (Si-face CMP Epi-ready); <1 nm (C- face Optical polish)

FWHM

A<30 arcsec B/C/D <50 arcsec

Micropipe Density

A+≤1cm-2  A≤10cm-2   B≤30cm-2  C≤50cm-2  D≤100cm-2

Surface Orientation

On axis± 0.5°

Off axis                         3.5° toward± 0.5°

Primary flat orientation

Parallel {1-100} ± 5°

Primary flat length

16.00 ± 1.70 mm

Secondary flat orientation

Si-face:90° cw. from orientation flat ± 5°

C-face:90° ccw. from orientation flat ± 5°

Secondary flat length

8.00 ± 1.70 mm

Surface Finish

Single or double face polished

Packaging

Single wafer box or multi wafer box

Usable area

≥ 90 %

Edge exclusion

1 mm


HPSI 4H SEMI-INSULATING SIC, 3″WAFER SPECIFICATION

SUBSTRATE PROPERTY

S4H-76-N-PWAM-330               S4H-76-N-PWAM-430

Description

A/B Production Grade  C/D Research Grade  D Dummy Grade   4H SiC Substrate

Polytype

4H

Diameter

(76.2 ± 0.38) mm

Thickness

(350 ± 25) μm                            (500 ± 25) μm

Carrier Type

semi-insulating

Dopant

V

Resistivity (RT)

>1E5 Ω·cm

Surface Roughness

< 0.5 nm (Si-face CMP Epi-ready); <1 nm (C- face Optical polish)

FWHM

A<30 arcsec B/C/D <50 arcsec

Micropipe Density

A+≤1cm-2  A≤10cm-2   B≤30cm-2  C≤50cm-2  D≤100cm-2

TTV/Bow /Warp

25μm

Surface Orientation

On axis

± 0.5°

Off axis

4°or 8° toward± 0.5°

Primary flat orientation

±5.0°

Primary flat length

22.22 mm±3.17mm
0.875″±0.125″

Secondary flat orientation

Si-face:90° cw. from orientation flat ± 5°

C-face:90° ccw. from orientation flat ± 5°

Secondary flat length

11.00 ± 1.70 mm

Surface Finish

Single or double face polished

Packaging

Single wafer box or multi wafer box

Scratch

None

Usable area

≥ 90 %

Edge exclusion

2mm


HPSI 4H SEMI-INSULATING SiC, 4″WAFER SPECIFICATION

SUBSTRATE PROPERTY

S4H-100-SI-PWAM-350               S4H-100-SI-PWAM-500

Description

A/B Production Grade  C/D Research Grade  D Dummy Grade   4H SiC Substrate

Polytype

4H

Diameter

(100 ± 0.5) mm

Thickness

(350 ± 25) μm                            (500 ± 25) μm

Carrier Type

Semi-insulating

Dopant

V

Resistivity (RT)

>1E5 Ω·cm

Surface Roughness

< 0.5 nm (Si-face CMP Epi-ready); <1 nm (C- face Optical polish)

FWHM

A<30 arcsec B/C/D <50 arcsec

Micropipe Density

A≤5cm-2   B≤15cm-2  C≤50cm-2  D≤100cm-2

TTV/Bow /Warp

TTV10μm;TTV 25μm;WARP45μm

Surface Orientation

On axis

± 0.5°

Off axis

None

Primary flat orientation

±5.0°

Primary flat length

32.50 mm±2.00mm

Secondary flat orientation

Si-face:90° cw. from orientation flat ± 5°

C-face:90° ccw. from orientation flat ± 5°

Secondary flat length

18.00 ± 2.00 mm

Surface Finish

Double face polished

Packaging

Single wafer box or multi wafer box

Scratches

<8 scratches to 1 x wafer diameter with total cumulative length

Cracks

None

Usable area

≥ 90 %

Edge exclusion

2mm


About Xiamen Powerway Advanced Material Co., Ltd

Found in 1990, Xiamen Powerway Advanced Material Co., Ltd (PAM-XIAMEN) is a leading manufacturer of compound semiconductor material in China. PAM-XIAMEN develops advanced crystal growth and epitaxy technologies, manufacturing processes, engineered substrates and semiconductor devices. PAM-XIAMEN's technologies enable higher performance and lower cost manufacturing of semiconductor wafer.


About SiC Substrate

Silicon carbide (SiC) has the potential to replace conventional semiconductors in high frequency and high power applications such as in pulse-width modulated electric vehicles, smart grids and next generation efficient power electronics. SiC advantages over silicon, the current industry standard, include high saturation velocity (high current), wide band gap (high voltages and temperature), both of which enable minimization of parasitic capacitances and reduction of active cooling, leading to transformational architectural improvements in power electronics. While the device structures have been well optimized, other challenges in SiC technology remain, and revolve around material quality. Research in the past few years has focused on growing high-quality single crystal SiC substrates and epi layers with low densities of structural defects. In addition to the high structural quality there are other requirements that must be met for these epi layers to be useful in high frequency and high power devices. In a power transistor chip the metalized backside and fingers on the epitaxial side introduce a passive parasitic capacitance, along with the active capacitive part of the device, limiting the performance at high frequencies. This parasitic capacitance can be minimized by using semi-insulating (SI) epi layers/substrates. One of the methods for introducing SI property to the substrate is to use vanadium as a deep level dopant to pin the Fermi level near mid bandgap. Although this is the original conceived method for producing commercial SI substrates, vanadium degrades crystal quality supported by increased FWHM of X-ray diffraction rocking curves.


Key Words: sic substrate manufacturers,cree sic wafers,silicon carbide wafer price,sic epitaxy,

wolfspeed,High-purity semi insulating,HPSI,4H-SiC,seeded sublimation,PVT,

SIMS,EPR,OAS,DLTS,Hall effect,Resistivity,thermal conductivity


For more information, please visit our website: http://www.semiconductorwafers.net,

send us email at angel.ye@powerwaywafer.com or powerwaymaterial@gmail.com

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