This paper describes the bonding characteristics of 3C-SiC wafers using plasma enhanced chemical vapor deposition (PECVD) oxide and hydrofluoric acid (HF) treatment for SiC-on-insulator (SiCOI) structures and high-temperature microelectromechanical system (MEMS) applications. In this work, insulator layers were formed on a heteroepitaxial 3C-SiC film grown on a Si (0 0 1) wafer by thermal wet oxidation and a PECVD process, successively. The pre-bonding of two polished PECVD oxide layers was made under definite pressure after the treatment of hydrophilic surface activation in HF. The bonding processes were carried out under various HF concentration and external applied pressure. The bonding characteristics were evaluated by the effects of HF concentration used in the surface treatment on the roughness of the oxide and the pre-bonding strength, respectively. Hydrophilic character of the oxidized 3C-SiC film surface was investigated by attenuated total reflection Fourier transformed infrared spectroscopy (ATR-FTIR). The root-mean-square (RMS) surface roughness of the oxidized 3C-SiC layers was measured by atomic force microscope (AFM). The strength of the bonded wafer was measured by tensile strength meter (TSM). The bonded interface was also analyzed by scanning electron microscope (SEM). The values of the bonding strength ranged from 0.52 to 1.52 MPa according to HF concentrations without the external applied load during pre-bonding process. The bonding strength initially increases with increasing HF concentration and reaches the maximum at 2.0% of HF concentration and then decreases. Consequently, low temperature 3C-SiC wafer direct bonding technique using a PECVD oxide layer and HF could be applied as a fabrication process of high quality substrates for high performance electronic devices and harsh environment MEMS applications. Keywords 3C-SiC; Wafer bonding; PECVD oxide; HF; High temperature; MEMS Source:Sciencedirect For more information, please visit our website:www.powerwaywafer.com, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com.
Highlights •High-quality InSb was grown on GaAs by MBE using a “buffer-free” method. •The strain energy is relieved by interfacial misfit dislocations observed by TEM. •The type and separation of dislocations are consistent with theoretical prediction. •InSb film is 98.9% relaxed and owns surface with roughness of 1.1 nm. •InSb film shows 33,840 cm2/V s room temperature electron mobility We report a fully relaxed low threading dislocation density InSb layer grown on a GaAs substrate using self-assembled periodic interfacial misfit dislocations. The InSb layer was grown at 310 °C by molecular beam epitaxy. The AFM measurement exhibited a root mean square (r.m.s.) roughness of 1.1 nm. ω−2θ scan results from x-ray diffraction measurement indicated that the InSb layer is 98.9% relaxed. Images from the transmission electron microscope measurement showed a threading dislocation density of 1.38×108 cm−2. The formation of highly uniform interfacial misfit dislocation array was also observed and the separation of dislocations is consistent with theoretical calculation. The InSb layer exhibited a 33,840 cm2/V s room temperature electron mobility. Keywords Thin films; Epitaxial Growth; TEM; Structural; Semiconductors；GaAs wafer,InSb wafer Source:Sciencedirect For more information, please visit our website:www.powerwaywafer.com, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com .
Highlights •Novel growth strategy of GaAs on Si(1 0 0) with AlAs/GaAs strain layer superlattice. •Emphasis on understanding the inconclusive crystalline morphology at initial layers. •Observed low TD in HRTEM and low RMS in AFM. •Observed fourth order of superlattice peaks in ω–2θ scan in HRXRD. •SAEDP shows fcc lattice and RSM study proves fully relaxed, un-tilted GaAs epilayer. A novel growth strategy for GaAs epilayer on Si(1 0 0) has been developed with AlAs/GaAs strained layer superlattice to achieve high crystalline quality for device applications. Emphasis has been given on understanding the inconclusive crystalline morphology of the initial layers by comprehensive material characterization. The influence of growth conditions have been studied by varying the growth temperatures, rates and V/III flux ratios. In-situ RHEED observations throughout the growth guided us to recognize the impact of individual growth parameters on the crystalline morphology. All the four stages of growth have been carried out by molecular beam epitaxy. The optimization of growth parameters at every stage initiates the formation of GaAs face centered cubic crystal from the very beginning. Material characterizations include AFM, HRTEM and HRXRD. The latter one, for the first time witnessed the intensity of superlattice satellite peaks in the fourth order. Low values of threading dislocation propagating to the top surface have been seen in HRTEM with absence of anti-phase boundaries (APB). Results for extended dislocations and surface roughness have been observed to be in the order of 106 cm−2 and 2 nm, respectively which is among the best reported values till date. Significant reduction of extended dislocations has been observed under strain fields in the superlattice. Notably, lower alloy mixing due to the optimized growth of AlAs/GaAs resulted in a suitable thermal behavioral platform as required for device applications. Fully relaxed, un-tilted, APB free, single domain and smooth GaAs epilayers have been achieved which paves the pathway to on-wafer integration of high performance III-Arsenide devices with Si logic circuits. Keywords A3. MBE; GaAs on Si(1 0 0); AlAs/GaAs superlattice; RSM; SAED pattern Source:Sciencedirect For more information, please visit our website:www.powerwaywafer.com, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com.
Highlights •The thickness of graphene grown on SiC was determined by AES depth profiling. •The AES depth profiling verified the presence of buffer layer on SiC. •The presence of unsaturated Si bonds in the buffer layer has been shown. •Using multipoint analysis thickness distribution of the graphene on the wafer was determined. Auger electron spectroscopy (AES) depth profiling was applied for determination of the thickness of a macroscopic size graphene sheet grown on 2 in. 6H-SiC (0 0 0 1) by sublimation epitaxy. The measured depth profile deviated from the expected exponential form showing the presence of an additional, buffer layer. The measured depth profile was compared to the simulated one which allowed the derivation of the thicknesses of the graphene and buffer layers and the Si concentration of buffer layer. It has been shown that the graphene-like buffer layer contains about 30% unsaturated Si. The depth profiling was carried out in several points (diameter 50 μm), which permitted the constructing of a thickness distribution characterizing the uniformity of the graphene sheet. Keywords Graphene on SiC; Buffer layer composition; AES depth profiling; Graphene thickness; Sublimation epitaxy Source:Sciencedirect For more information, please visit our website:www.powerwaywafer.com, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com.
Highlights •AlGaN/GaN HEMT on SiC substrate is presented to improve the electrical operation. •The depletion region of structure is amended using a multiple recessed gate. •A gate structure is proposed to be able to control the thickness of the channel. •RF parameters are considered and are improved. In this paper, a high performance AlGaN/GaN High Electron Mobility Transistor (HEMT) on SiC substrates is presented to improve the electrical operation with the amended depletion region using a multiple recessed gate (MRG–HEMT). The basic idea is to change the gate depletion region and a better distribution of the electric field in the channel and improve the device breakdown voltage. The proposed gate consists of lower and upper gate to control the channel thickness. Also, the charge of the depletion region will change due to the optimized gate. In addition, a metal between the gate and drain including the horizontal and vertical parts is used to better control the thickness of the channel. The breakdown voltage, maximum output power density, cut-off frequency, maximum oscillation frequency, minimum noise figure, maximum available gain (MAG), and maximum stable gain (MSG) are some parameters for designers which are considered and are improved in this paper. A high performance AlGaN/GaN High Electron Mobility Transistor (HEMT) on SiC substrates is presented to improve the electrical operation with the amended depletion region. Keywords AlGaN/AlN/GaN/SiC HEMT; Electric field; Depletion region; RF applications Source:Sciencedirect For more information, please visit our website:www.powerwaywafer.com, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com.
Highlights •The barrier controlled trapping model was developed around extended defects. •Electron mobility and E-field distribution were distorted by space charge depletion region. •Extended defects act as a recombination-activated region. •The relationships between extended defects and detector performance were established. Transient current techniques using alpha particle source were utilized to study the influence of extended defects on the electron drift time and the detector performance of CdZnTe crystals. Different from the case of trapping through isolated point defect, a barrier controlled trapping model was used to explain the mechanism of carrier trapping at the extended defects. The effect of extended defects on the photoconductance was studied by laser beam induced transient current (LBIC) measurement. The results demonstrate that the Schottky-type depletion space charge region is induced at the vicinity of the extended defects, which further distorts the internal electric field distribution and affects the carrier trajectory in CdZnTe crystals. The relationship between the electron drift time and detector performance has been established. Keywords II–VI semiconductor devices; CdZnTe; Barrier controlled trapping; Extended defects Source:Sciencedirect For more information, please visit our website:www.powerwaywafer.com, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com.
Highlights •We fabricated HV AlGaN/GaN-on-Si HEMTs with Schottky and ohmic drain electrodes. •We examine impact of temperature on the electrical parameters of fabricated devices. •The use of Schottky drain contacts increase the breakdown voltage from 505 to 900 V. •The SD-HEMTs are characterized by lower increase of Ron with increasing temperature. Abstract In this work we present results of electrical parameters characterization of high-voltage AlGaN/GaN high electron mobility transistors with ohmic and Schottky drain electrodes on silicon substrates. The use of Schottky-drain contacts improves breakdown voltage (VBR ), which was VBR = 900 V for LGD = 20 μm in contrast to VBR = 505 V for ohmic-drain contacts. Both types of transistors exhibit drain current density of 500 mA/mm and leakage current of 10 μA/mm. Temperature-dependent characterization reveals a drain current density decrease with increasing temperature. The Schottky-drain HEMTs are characterized by lower increase of the Ron (ΔRon = 250% at 200 °C) in comparison to ohmic drain contacts (ΔRon = 340% at 200 °C) relative to the room temperature due to decrease of on-set voltage of Schottky-drain HEMTs. Keywords AlGaN/GaN-on-silicon; Power devices; HEMT; Schottky drain Source:Sciencedirect For more information, please visit our website:www.powerwaywafer.com, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com.
Highlights •Porous GaN template was prepared by electrochemical and photoelectrochemical etching scheme. •InGaN/GaN light-emitting diode (LED) structure was overgrown on the etched GaN template. •Overgrown GaN films and LEDs showed lower strain and lower density of surface defects. •The overgrown LED structures showed enhanced electroluminescence efficiency. Porous GaN templates were prepared by combined electrochemical etching (ECE) and back-side photoelectrochemical etching (PECE), followed by the overgrowth of GaN films and InGaN/GaN multiple quantum well (MQW) light-emitting diode (LED) structures. Structural, luminescent, and electrical properties of the GaN and LED structures were studied and compared with the properties of structures grown under the same conditions on templates not subjected to ECE–PECE treatment. Overgrowth of LED structures on the ECE–PECE templates reduced strain, cracking, and micropits, leading to increased internal quantum efficiency and light extraction efficiency. This luminescence enhancement was observed in overgrown GaN films, but was more pronounced for InGaN/GaN LED structures due to suppression of piezoelectric polarization field in QWs. Keywords Electrochemical etching; Photo-electrochemical etching; Porous GaN; Light-emitting diodes Source:Sciencedirect For more information, please visit our website:www.powerwaywafer.com, send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com.
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